1. Field of the Invention
The present invention relates to a clock generator for generating a plurality of clocks independently adjusted in phase using a received external clock, and to a semiconductor device having the clock generator therein. More particularly, this invention is concerned with a semiconductor device for correcting a time difference of each input data from a data fetching edge of an external clock.
2. Description of the Related Art
In a large-scale semiconductor device system such as a computer using semiconductor devices, each part of the system is designed to operate synchronously with a clock. Input or output of a signal such as a data signal or address signal is synchronous with the clock. Because of a difference in characteristic of an output circuit in a driving-side semiconductor device from another output circuit or a phase difference of an output timing signal, the state transition edge of each output signal becomes different in time from the trailing edge of the clock. Moreover, since the length of a signal line may be different from that of another line or the load on the signal line may be different from that on another line, there arises a difference in transfer time between signals. A time difference of the state transition edge of an input signal received by a receiving-side semiconductor device from the trailing edge of the clock gets larger. During a period during which the time difference occurs, all input signals are uncertain. The period is therefore regarded as an uncertain period during which any input signal cannot be fetched. The time difference in phase between signals is referred to as a skew. The skew depends on the length of or load on a signal line and therefore cannot be nullified.
When a semiconductor device fetches an input signal using a latch, a required setup time and hold time must be set in the latch from the operational viewpoint. A time during which an input signal must be certain is defined before and after the leading edge of a clock. Even if an input signal to be received by a receiving-side semiconductor device has a skew, the input signal must be certain during the setup time and hold time before and after the leading edge of the clock. A period remaining after subtraction of an uncertain period of the input signal from the cycle of the clock is a certain period of the input signal. In a low-speed system, the uncertain period of the input signal is relatively small for the cycle of a clock and therefore does not pose a serious problem. However, in a high-speed system, since the cycle of a clock is very short, the ratio of the uncertain period of an input signal to the cycle of the clock gets relatively large. The certain period diminishes accordingly. The uncertain period therefore poses a serious problem. This may lead to a situation in which a skew restricts the operating speed of a semiconductor device.
For solving this kind of problem, an art in which an input timing adjustment circuit and a re-synchronization circuit are installed for each input signal and all input signals are adjusted to be mutually synchronous is conceivable. The input timing adjustment circuit includes a delay-locked loop (DLL). A delay circuit included in the delay-locked loop includes a delay line having numerous delay elements, each of which introduces a magnitude of delay equivalent to the passage of a signal through one stage, connected in series with one another. When the magnitude of delay per stage is reduced in order to enable precise phase adjustment, a phase must be able to be adjusted by a quantity large enough to cancel a predicted skew. The number of stages of the delay line therefore becomes very large. For this reason, the scale of the delay circuit is large. Moreover, this kind of delay circuit must be installed for each input signal. The whole of a circuit for coping with the skews of the input signals therefore becomes very large in scale. This dominates the area of a chip and becomes a cause for an increase in chip area.